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lt3992 1 3992f typical a pplica t ion fea t ures a pplica t ions descrip t ion monolithic dual tracking 3a step-down switching regulator the lt ? 3992 is a dual current mode pwm step-down dc/dc converter with two internal 4.6a switches. inde- pendent input voltage, shutdown, feedback, soft-start, uvlo current limit and comparator pins for each channel simplify complex power supply tracking and sequencing requirements. to optimize efficiency and component size, both convert - ers have a programmable maximum current limit and are synchronized to either a common external clock input, or a resistor settable fixed 250khz to 2mhz internal oscillator. a frequency divider is provided for channel 1 to further optimize component size. at all frequencies, a 180 phase relationship between channels is maintained, reducing volt- age ripple and component size. a clock output is available for synchronizing multiple regulators. minimum input to output voltage ratios are improved by allowing the switch to stay on through multiple clock cycles only switching off when the boost capacitor needs recharg- ing. independent channel operation can be programmed using the shdn pin. disabling both converters reduces the total quiescent current to <10a. l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 12v and 5v 2-stage multi-frequency step-down converter n wide input range: C operation from 3v to 60v n independent supply, shutdown, soft-start, uvlo, programmable current limit and programmable power good for each 3a regulator n die temperature monitor n adjustable/synchronizable fixed frequency operation from 250khz to 2mhz with synchronized clock output n independent synchronized switching frequencies optimize component size n antiphase switching n outputs can be paralleled n flexible output voltage t racking n low dropout: 95% maximum duty cycle n 5mm 5mm qfn package n fmea compliant 38-pin exposed pad tssop package n automotive supplies n distributed supply regulation independent synchronized switching frequencies extend full frequency input range bst1 sw1 v out1 cmpi1 cmpo1 ss1 ilim1 rt/sync div v c1 fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 clkout v c2 t j fb2 ind2 3992 ta01a bst2 shdn1 shdn2 v in1 v out2 lt3992 gnd v in2 4.7f v in1 15v to 60v v out2 5v 2a 1600khz v out1 12v 1a 400khz 100k pg 22h 2.2h 0.1f 0.1f 8.06k 102k 15k 100k 680pf 33pf 0.1f 48.7k 680pf 0.1f 33pf 60.4k 10k 42.2k fb1 10nf clkout 1600khz 8.06k 113k 22f 47f ch1 400khz 20v/div ch2 1.6mhz 5v/div v in = 60v 500ns/div 3992 ta01b
lt3992 2 3992f a bsolu t e maxi m u m r a t ings v in1/2 , shdn1/2, cmpo1/2 ....................................... 6 0v sw1/2 .................................................................... v in1/2 bst1/2 ...................................................................... 75 v bst1/2 pin above sw1/2 .......................................... 25 v ind1/2, v out1/2 ......................................................... 60v f b1/2, cmpi1/2, ss1/2 ................................................ 5v r t/sync ..................................................................... 5v di v, ilim1/2 ............................................................. 2. 5v (note 1) p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3992euh#pbf lt3992euh#trpbf 3992 32-lead (5mm 5mm) plastic qfn C40c to 125c lt3992iuh#pbf lt3992iuh#trpbf 3992 32-lead (5mm 5mm) plastic qfn C40c to 125c lt3992efe#pbf lt3992efe#trpbf lt3992fe 38-lead plastic tssop C40c to 125c lt3992ife#pbf lt3992ife#trpbf lt3992fe 38-lead plastic tssop C40c to 125c lt3992hfe#pbf lt3992hfe#trpbf lt3992fe 38-lead plastic tssop C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ v c1/2 , t j .............................................................. 10 0a operating junction temperature range (note 2) l t3992euh ........................................ C 40c to 125c lt 3992iuh ......................................... C 40c to 125c lt 3992efe ......................................... C 40c to 125c lt 3992ife .......................................... C 40c to 125c lt 3992hfe ........................................ C 40c to 150c storage temperature range .................. C 65c to 150c 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 gnd uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1bst1 cmpo1 cmpi1 fb1 fb2 cmpi2 cmpo2 bst2 ilim1 v c1 rt/sync clkout t j div v c2 ilim2 v out1 dnc* ind1 dnc* sw1 v in1 shdn1 ss1 v out2 dnc* ind2 dnc* sw2 v in2 shdn2 ss2 ja = 44c/w, jc(pad) = 7.3c/w exposed pad (pin 33) is gnd, must be soldered to pcb *do not connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 nc ind1 nc v out1 nc bst1 cmpo1 cmpi1 fb1 nc fb2 cmpi2 cmpo2 bst2 nc v out2 nc ind2 nc sw1 nc v in1 shdn1 ss1 i lim1 v c1 nc rt/sync clkout t j div vc2 i lim2 ss2 shdn2 v in2 nc sw2 39 gnd ja = 17.5c/w, jc(pad) = 10c/w exposed pad (pin 39) is gnd, must be soldered to pcb
lt3992 3 3992f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v vin1/2 = 15v unless otherwise specified. (note 2) parameter conditions min typ max units shdn voltage threshold ch1/2 l 1.24 1.32 1.4 v shdn input current ch1/2 v shdn = 1.35v C1 0 1 a v in1 undervoltage lockout (note 3) 2.6 2.9 3.2 v v in1 shutdown current v shdn = 0v l 6 13 a v in2 shutdown current v shdn = 0v l 0.1 2 a v in1 quiescent current v fb1/2 = 2v 3 4.2 6 ma v in2 quiescent current v fb1/2 = 2v 300 530 900 a feedback voltage ch1/2 v vc1/2 = 1v l 786 806 824 mv feedback voltage regulation v vin1/2 = 4v to 60v l 780 806 830 mv feedback voltage offset ch1 to ch2 v vc1/2 = 1v l C13 0 13 mv feedback bias current ch1/2 v vc1/2 = 1v l 0 85 300 na t j output voltage (note 4) t j = 25c, i tj = 25a, temperature = 25c i tj = 25a, temperature = 125c i tj = 25a, temperature = C40c 250 1.23 C380 mv v mv t j error temperature = 25c to 125c l C100 0 100 mv error amp g m ch1/2 v vc1/2 = 1v, i vc1/2 = 10a 250 350 450 mho error amp source current ch1/2 v fb1/2 = 0.7v, v vc1/2 = 1v 15 25 40 a error amp sink current ch1/2 v fb1/2 =0.9v, v vc1/2 = 1v 15 25 40 a error amp high clamp ch1/2 v fb1/2 = 0.7v 1.7 1.9 2.1 v error amp switching threshold ch1/2 v fb1/2 = 0v 0.8 1.0 1.2 v soft-start source current ch1/2 v fb1/2 = 2v, v ss1/2 = 0.07v l 9 13.5 17 a soft-start v oh ch1/2 v fb1/2 = 2.0v 1.9 2.15 2.4 v soft-start sink current ch1/2 v fb1/2 = 0.7v, v ss1/2 = 2v 0.4 0.9 2 ma soft-start v ol ch1/2 v fb1/2 = 0v 130 170 210 mv soft-start to feedback offset ch1/2 v vc1/2 = 1v, v ss1/2 = 0.4v l 16 0 16 mv ss por threshold ch1/2 70 110 140 mv soft-start sink current ch1/2 por v fb1/2 = 2v, v ss1/2 = 0.14v (note 5) 150 450 600 a soft-start sw disable ch1/2 v fb1/2 = 0v (note 5) 80 115 150 mv cmpi bias current ch1/2 v cmpi1/2 = 0.8v C100 0 100 na cmpo leakage ch1/2 v cmp1/2 = 0.8v, v cmpo1/2 = 60v 70 500 na cmpi threshold ch1/2 v cmpi1/2 rising l 690 725 760 mv cmpi threshold ch1/2 of v fb1/2 v cmpi1/2 rising (note 6) 86 90 94 % cmpi hysteresis ch1/2 v cmpi1/2 50 80 105 mv cmpo sink current ch1/2 v cmpi1/2 = 0.6v, v cmpo1/2 = 0.2v 150 250 a rt/sync reference current v rt/sync = 0.36v e- & i-grade l 11.3 12 12.7 a rt/sync reference current v rt/sync = 0.36v h-grade l 11.2 12 13 a minimum switching frequency r rt/sync =0 50 110 150 khz switching frequency r rt/sync = 28k 900 1 1100 khz maximum switching frequency r rt/sync =100k 2.2 2.5 3.0 mhz switching phase angle ch1 ch2 185 deg div reference current v div = 1v l 10.7 12 13.3 a ch1 div 2 threshold r rt/sync = 0v 0.44 0.5 0.56 v
lt3992 4 3992f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v vin1/2 = 15v unless otherwise specified. (note 2) parameter conditions min typ max units ch1 div 4 threshold r rt/sync = 0v 0.89 1.0 1.06 v ch1 div 8 threshold r rt/sync = 0v 1.39 1.5 1.56 v clkout v ol 0.25 v clkout v oh 2 v clkout to sw1on delay ( t dclkosw1 ) clkout rising 60 ns clkout to sw2on delay ( t dclkosw2 ) clkout falling 30 ns rt/sync to clkout delay ( t drtsynch ) v rt/sync = 0v to 2v rising edge 300 ns rt/sync to clkout delay ( t drtsyncl ) v rt/sync = 2v to 0v falling edge 150 ns sync frequency range 250 2000 khz sync phase angle ch1 to ch2 sync frequency = 250khz 180 deg minimum switch on-time ch1/2 160 ns minimum switch off-time ch1/2 200 ns minimum boost for 100% dc ch1/2 (note 7) 1.6 2.2 2.6 v ind + v out current ch1/2 v vout1/2 = 0v v vout1/2 = 5v 1.5 0.5 5 5 a a ilim1/2 reference current v ilim = 0v l 10 12 16 a ind to v out maximum current ch1/2 v ilim1/2 = 0.5v, v vout = 1v (note 8) v ilim1/2 = 0.5v, v vout = 5v (note 8) v ilim1/2 = 1.5v, v vout = 1v (note 8) v ilim1/2 = 1.5v, v vout = 5v (note 8) l l 0.5 0.7 3.5 3.5 1.5 1.8 4.6 4.6 3 3 6.4 6.4 a a a a switch leakage current ch1/2 v sw1/2 = 0v l 1 10 a switch saturation voltage ch1/2 i sw1/2 = 500ma, v bst1/2 = 18v i sw1/2 = 3a, v bst1/2 = 18v 200 325 mv mv boost current ch1/2 i sw1/2 = 500ma, v bst1/2 = 8v i sw1/2 = 3a, v bst1/2 = 8v 5 35 8 55 25 85 ma ma minimum boost voltage ch1/2 (note 9) i sw1/2 = 3a, v bst1/2 = 8v 1.0 2.2 3.0 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3992euh/lt3992efe is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3992iuh/lt3992ife is guaranteed over the full C40c to 125c operating junction temperature range. the lt3992hfe is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 3: v in undervoltage lockout is defined as the voltage which the v in pin must exceed for operation. the threshold guarantees that internal bias lines are regulated and switching frequency is constant. actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. see the applications information section. note 4: the t j output voltage represents the temperature at the center of the die while dissipating quiescent power. due to switch power dissipation and temperature gradients across the die, the t j output voltage measurement does not guarantee that absolute maximum junction temperature will not be exceeded. note 5: an internal power on reset (por) latch is set on the positive transition of the shdn1/2 pin through its threshold, thermal shutdown or overvoltage lockout. the output of the latch activates current sources on each ss pin which typically sink 450a and discharge the ss capacitor. the latch is reset when both ss pins are driven below the soft-start por threshold or the shdn pin is taken below its threshold. note 6: the threshold is expressed as a percentage of the feedback reference voltage for the channel. note 7: to enhance dropout operation, the output switch will be turned off for the minimum off-time only when the voltage across the boost capacitor drops below the minimum boost for 100% duty cycle threshold. note 8: the ind to v out maximum current is defined as the value of current flowing from the ind pin to the v out pin which resets the switch latch when the v c pin is at its high clamp. note 9: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch.
lt3992 5 3992f typical p er f or m ance c harac t eris t ics shutdown threshold and minimum input voltage vs temperature shutdown quiescent current vs temperature fb voltage and ch1-ch2 fb offset vs temperature t j output voltage vs temperature error amplifier transconductance vs temperature soft-start-to-feedback offset vs temperature comparator thresholds vs temperature temperature (c) ?50 voltage (v) 2.0 2.5 3.0 25 50 75 100 125 3992 g01 1.5 1.0 ?25 0 150 0.5 0 3.5 minimum input voltage shutdown threshold voltage temperature (c) ?50 0 current (a) 2 1 3 5 4 7 6 0 50 100 150 3992 g02 9 8 10 i q1 i q2 ?25 25 75 125 temperature (c) ?50 800 feedback voltage (mv) offset voltage (mv) 820 815 810 805 0 50 75 3992 g03 ?8 ?4 ?6 8 4 0 ?2 6 2 ?25 25 100 ch1 ch2 125 150 offset temperature (c) ?50 voltage (v) 0.50 1.00 150 3992 g04 0 ?0.50 0 50 100 ?25 25 75 125 1.50 0.25 0.75 ?0.25 1.25 r tj = 30k to gnd r tj = 30k to ?1v temperature (c) ?50 transconductance (mho) 295 385 400 415 10 50 70 90 3992 g05 265 355 325 280 370 250 340 310 ?30 ?10 30 130110 150 temperature (c) ?50 voltage (mv) 0 2 150 3992 g06 ?2 ?4 0 50 100 ?25 25 75 125 4 ?1 1 ?3 3 v ss = 0.4v temperature (c) ?50 630 voltage (mv) 640 660 670 680 730 700 0 50 75 3992 g07 650 710 720 690 ?25 25 100 125 150 rising threshold falling threshold comparator sink current vs temperature switching frequency vs temperature temperature (c) ?50 current (a) 200 300 150 3992 g08 100 0 0 50 100 ?25 25 75 125 400 150 250 50 350 sink current at v cmpo = 0.4v temperature (c) ?50 frequency (khz) 1000 1200 1400 150 3992 g09 800 400 600 0 0 50 100 ?25 25 75 125 200 1800 1600 r rt/sync = 44.2k r rt/sync = 28.0k r rt/sync = 13.0k r rt/sync = 0k
lt3992 6 3992f typical p er f or m ance c harac t eris t ics switching phase vs temperature clkout-to-sw1 delay vs temperature rt/sync-to-clkout and sw1 delay vs temperature synchronization duty cycles vs temperature div voltage threshold vs temperature switch saturation voltage vs temperature boost current vs temperature minimum boost voltage vs temperature switch peak current vs temperature temperature (c) ?50 phase (deg) 187 191 150 3992 g10 183 181 179 175 0 50 100 ?25 25 75 125 195 185 189 177 193 temperature (c) ?50 60 delay (ns) 70 90 100 110 160 130 0 50 75 3992 g11 80 140 150 120 ?25 25 100 125 150 temperature (c) ?50 delay (ns) 250 300 350 150 3992 g12 200 150 0 0 50 100 ?25 25 75 125 100 50 450 400 sw1 clkout temperature (c) ?50 0 duty cycle (%) 10 30 40 50 100 70 0 50 75 3992 g13 20 80 90 60 ?25 25 100 125 150 rt/sync frequency = 1mhz maximum rt/sync duty cycle minimum rt/sync duty cycle temperature (c) ?50 voltage (v) 1.0 1.2 1.4 150 3992 g14 0.8 0.6 0 0 50 100 ?25 25 75 125 0.4 0.2 1.8 1.6 8 4 2 temperature (c) ?50 100 voltage (mv) 150 200 250 300 0 50 100 150 3992 g15 350 400 ?25 25 75 125 i sw = 3a i sw = 1a i sw = 500ma temperature (c) ?50 0 boost current (ma) 10 30 40 50 100 70 0 50 75 3992 g16 20 80 90 60 ?25 25 100 125 150 0.5a 1a 3a temperature (c) ?50 0 peak current (a) 0.5 1.5 2.0 2.5 5.0 3.5 0 50 75 3992 g17 1.0 4.0 4.5 3.0 ?25 25 100 125 150 v ilim = 1.5v v ilim = 0.5v temperature (c) ?50 voltage (v) 2.00 2.50 150 3992 g18 1.50 1.00 0 50 100 ?25 25 75 125 3.00 1.75 2.25 1.25 2.75 i sw = 3a
lt3992 7 3992f typical p er f or m ance c harac t eris t ics clkout frequency vs rt/sync resistance 5v efficiency 3.3v efficiency rt/sync resistance (k) 0 0 clkout frequency (khz) 250 500 750 1500 1750 2000 2250 2500 20 40 50 80 3992 g19 1000 1250 10 30 60 70 output current (a) 0 50 efficiency (%) 70 75 80 90 1.0 2.0 2.5 3992 g20 65 60 55 85 0.5 1.5 3.0 3.5 v in = 12v v in = 24v v in = 36v f sw = 1mhz ch1 = 5v ch2 = 3.3v, 0a output current (a) 0 50 efficiency (%) 70 75 80 90 1.0 2.0 2.5 3992 g21 65 60 55 85 0.5 1.5 3.0 3.5 v in = 12v v in = 24v f sw = 1mhz ch1 = 5v, 0a ch2 = 3.3v 5v efficiency 3.3v efficiency output current (a) 0 40 efficiency (%) 70 75 80 90 1.0 2.0 2.5 3992 g22 65 60 45 50 55 85 0.5 1.5 3.0 3.5 f sw = 500khz ch1 = 5v ch2 = 3.3v, 0a v in = 12v v in = 24v v in = 36v v in = 48v v in = 60v output current (a) 0 40 efficiency (%) 70 75 80 90 1.0 2.0 2.5 3992 g23 65 60 45 50 55 85 0.5 1.5 3.0 3.5 f sw = 500khz ch1 = 5v, 0a ch2 = 3.3v v in = 12v v in = 24v v in = 36v v in = 48v
lt3992 8 3992f p in func t ions bst1/2: the bst pin provides a higher than v in base drive to the power npn to ensure a low switch drop. if the voltage between the bst pin and the v in pin is less than the voltage required to fully turn on the power npn, the power switch is turned off to recharge the bst capacitor. cmpi1/2: the cmpi pin is an input to a comparator with a threshold of 725mv and 80mv of hysteresis. connecting the cmpi pin to the fb pin will generate a power good signal when the output is within 90% of its regulated value. cmpo1/2: the cmpo pin is an open-collector output that sinks current when the cmpi pin falls below its threshold. for a typical input voltage above 2.9v, its output state re - mains true, although during shutdown, v in1 undervoltage lockout or thermal shutdown, its current sink capability is reduced. the compo pins can be left open circuit or tied together to form a single power good signal. div: the voltage present at the div pin determines the ratio of channel 1 frequency to the master clock frequency set by the rt/sync pin. the div pin is driven by an internal current source with a typical value of 12a which allows a single resistor from the div pin to ground to set the div voltage and resulting channel 1 frequency divider. ratios of 1, 2, 4 and 8 are available. see the applications information section for more information. dnc: do not connect. gnd: the exposed pad pin is the only ground connec- tion for the device. the exposed pad should be soldered to a large copper area to reduce thermal resistance. the gnd pin is common to both channels and also serves as small-signal ground. for ideal operation all small-signal ground paths should connect to the gnd pin at a single point avoiding any high current ground returns. fb1/2: the fb pin is the negative input to the error amplifier. the output switches to regulate this pin to 806mv with respect to the exposed ground pad. bias current flows out of the fb pin. ilim1/2: the voltage present at the ilim pin determines the peak inductor current for the channel. the ilim pin is driven by an internal current source with a typical value of 12a. a resistor from the ilim pin to ground sets the ilim voltage; the resistor value must be between 42.2k and 120k. the maximum current limit range is 4.8a to 1.8a when the ilim voltages are 1v and 0.5v respectively. ind1/2: the ind pin is the input to the internal sense resistor that measures current flowing in the inductor. when the current in the resistor exceeds the current dictated by the v c pin, the sw latch is held in reset, disabling the output switch. bias current flows out of the ind pin. rt/sync: the voltage present at the rt/sync pin deter - mines the constant switching frequency. the rt/sync pin is driven by an internal current source with a typical value of 12a which allows a single resistor from the rt/ sync pin to ground to set the rt/sync voltage and result - ing switching frequency. minimum switching frequency is typically 110khz when v rt/sync is 0v and maximum switching frequency is typically 2.5mhz when v rt/sync is above 950mv. driving the rt/sync pin with an external clock signal will synchronize the switch to the applied frequency. synchro - nization occurs on the rising edge of the clock signal after the clock signal is detected. each rising clock edge initiates an oscillator ramp reset. a gain control loop servos the oscillator charging current to maintain constant oscillator amplitude. hence, the slope compensation and channel phase relationship remain unchanged. if the clock signal is removed, the oscillator reverts to resistor mode after the synchronization detection circuitry times out. the clock source impedance should be set such that the current out of the rt/sync pin in resistor mode generates a frequency roughly equivalent to the synchronization frequency. see the applications information section for more information.
lt3992 9 3992f pin f unc t ions shdn1/2: the shutdown pin is used to control each channels operation. in addition to controlling channel 1, the shdn1 pin also activates control circuitry for both channels and must be present for channel 2 to operate. when shdn1 is below its threshold, quiescent current is reduced to a typical value of 6a. independent channel uvlo can be programmed by connecting the shdn pin to an input voltage divider. see the applications information section for more information. if the shutdown features are not used, the shdn pin should be tied to v in . ss1/2: current flowing out the ss pin into an external capacitor defines the rise time of the output voltage. when the ss pin is lower than the 0.806v reference, the feedback is regulated to the ss voltage. when the ss pin exceeds the reference voltage, the output will regulate the fb pin voltage to 0.806v and the ss pin will continue to rise until its clamp voltage. during an output overload, the v c pin is driven above the maximum switch current level activating its voltage clamp. when the v c clamp is activated, the ss pin is discharged until the output reaches a regulation point that the maximum output current can maintain. when the overload condition is removed, the output soft starts from that voltage. in the case of a shdn or thermal shutdown event, a power on reset latch ensures the capacitors on both channels are fully discharged before either is released. connecting both ss pins together ensures the outputs track together. clkout: the clkout pin generates a square wave of 0v to 2.5v which is synchronized to the internal oscillator. if the switching frequency is set by an external resistor the resultant clock duty cycle will be 50%. if the rt/sync pin is driven by an external clock source, the resultant clkout duty cycle will mirror the external source. sw1/2: the sw pin is the emitter of the internal power npn. at switch off, the inductor will drive this pin below ground with a high dv/dt. an external schottky catch diode to ground, close to the sw pin and respective v in decoupling capacitors ground, must be used to prevent this pin from excessive negative voltages. t j : the t j pin outputs a voltage proportional to junction temperature. the pin is 250mv for 25c and has a slope of 10mv/c. see the applications information section for more information. v c1/2 : the v c pin is the output of the error amplifier and the input to the peak switch current comparator. it is normally used for frequency compensation, but can also be used as a current clamp or control loop override. if the error amplifier drives v c above the maximum switch current level, a voltage clamp activates. this indicates that the output is overloaded and current is pulled from the ss pin reducing the regulation point. v in1 : the v in1 pin powers the internal control circuitry for both channels and is monitored by an undervoltage lockout comparator. the v in1 pin is also connected to the collector of channel 1s on-chip power npn switch. the v in1 pin has high di/dt edges and must be decoupled to ground close to the pin of the device. v in2 : the v in2 pin powers the output stage for channel 2 and is monitored by an undervoltage lockout comparator. v in1 voltage must be greater than typically 2.9v for v in2 operation. the v in2 pin is also the collector of channel 2s on-chip power npn switch. the v in2 pin has high di/ dt edges and must be decoupled to ground close to the pin of the device. v out1/2 : the v out pin is the output to the internal sense resistor that measures current flowing in the inductor. when the current in the resistor exceeds the current dic- tated by the v c pin, the sw latch is held in reset disabling the output switch. bias current flows out of the v out pin.
lt3992 10 3992f b lock diagra m figure 1. lt3992 block diagram the lt3992 is a dual channel, constant frequency, current mode buck converter with internal 4.6a switches. each channel can be independently controlled with the exception that v in1 must be above the typically 2.9v undervoltage lockout threshold to power the common internal regulator, oscillator and thermometer circuitry. if the shdn1 pin is taken below its 1.32v threshold the lt3992 will be placed in a low quiescent current mode. in this mode the lt3992 typically draws 6a from v in1 and <1a from v in2 . when the shdn pin is driven above 1.32v, the internal bias circuits turn on generating an internal regulated voltage, 0.806v fb , 12a rt/sync, div and ilim current references, and a por signal which sets the soft-start latch. once the internal reference reaches its regulation point, the internal oscillator will start generating a master clock signal for the two regulators at a frequency determined by the voltage present at the rt/sync pin. the channel 1 clock is then divided by 1, 2, 4 or 8 depending on the voltage present at the div pin. channel 2s clock runs at the master clock frequency with a 180 phase shift from channel 1. alternatively, if a synchronization signal is detected by the lt3992 the rt/sync pin, the master clock will be generated at the incoming frequency on the rising edge of the synchronization pulse with channel 1 in phase with the synchronization signal. frequency division and phase remains the same as the internally generated master clock. in addition, the internal slope compensation will be au- tomatically adjusted to prevent subharmonic oscillation during synchronization. in either mode of oscillator op- eration, a square wave with the master clock frequency, synchronized to channel 1 is present at the clkout pin. the two regulators are constant frequency, current mode step-down converters. current mode regulators are con- trolled by an internal clock and two feedback loops that 2.9v 3992 f01 + ? v in1 + ? + ? + + ? 1.32v thermal shutdown v in1 shdn1 ss1 v c1 110mv + ? 12a 2.5v 12a 2.5v ilim1 r lim pre slope compensation driver circuitry dropout enhancement channel 1 oscillator and agc internal regulator and references clk2 to channel 2 master clock clk1 0.806v 2.5v 0.72v s q r + ? pre s q r 12a 2.5v rt/sync 12a 2.5v div r3 r div bst1 sw1 ind1 fb1 r1 r2 cmpi1 cmpo1 t j clkout gnd v out1 v in1 + ?
lt3992 11 3992f b lock diagra m control the duty cycle of the power switch. in addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. this technique means that the error amplifier commands current to be delivered to the output rather than voltage. a voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180 shift will occur. the current fed sys - tem will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the lc resonant frequency. this makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. the block diagram in figure 1 shows only one of the switching regulators whose operation will be discussed below. the additional regulator will operate in a similar manner with the exception that its clock will be 180 out of phase with the other regulator. when, during power-up, an internal por signal sets the soft-start latch, both ss pins will be discharged to ground to ensure proper start-up operation. when the ss pin voltage drops below 110mv, the v c pin is driven low disabling switching and the soft-start latch is reset. once the latch is reset the soft-start capacitor starts to charge with a typical value of 12a. as the voltage rises above 110mv on the ss pin, the v c pin will be driven high by the error amplifier. when the voltage on the v c pin exceeds 1v, the clock set-pulse sets the driver flip-flop, which turns on the internal power npn switch. this causes current from v in , through the npn switch, inductor and internal sense resistor to increase. when the voltage drop across the internal sense resistor exceeds a predetermined level set by the voltage on the v c pin, the flip-flop is reset and the internal npn switch is turned off. once the switch is turned off the inductor will drive the voltage at the sw pin low until the external schottky diode starts to conduct, decreasing the current in the inductor. the cycle is repeated with the start of each clock cycle. however, if the internal sense resistor voltage exceeds the predetermined level at the start of a clock cycle, the flip-flop will not be set resulting in a further decrease in inductor current. since the output current is controlled by the v c voltage, output regulation is achieved by the error amplifier continually adjusting the v c pin voltage. the error amplifier is a transconductance amplifier that compares the fb voltage to the lowest voltage present at either the ss pin or an internal 806mv reference. compen- sation of the loop is easily achieved with a simple capacitor or series resistor/capacitor from the v c pin to ground. the regulators maximum output current occurs when the v c pin is driven to its maximum clamp value by the error amplifier. the value of the typical maximum switch current can be programmed from 4.6a to 1.8a by placing a resistor from the ilim pin to ground. since the ss pin is driven by a constant current source, a single capacitor on the soft-start pin will generate controlled linear ramp on the output voltage. if the current demanded by the output exceeds the maxi - mum current dictated by the v c pin clamp, the ss pin will be discharged, lowering the regulation point until the output voltage can be supported by the maximum current. once the overload condition is removed, the regulator will soft-start from the overload regulation point. shutdown control or thermal shutdown will set the soft- start latch, resulting in a complete soft-start sequence. the switch driver operates from either the v in or bst volt- age. an external diode and capacitor are used to generate a drive voltage higher than v in to saturate the output npn and maintain high efficiency. if the bst capacitor voltage is sufficient, the switch is allowed to operate to 100% duty cycle. if the boost capacitor discharges towards a level insufficient to drive the output npn, a bst pin compara- tor forces a minimum cycle off time, allowing the boost capacitor to recharge. a comparator with a threshold of 720mv and 80mv of hysteresis is provided for detecting error conditions. the cmpo output is an open-collector npn that is off when the cmpi pin is above the threshold allowing a resistor to pull the cmpo pin to a desired voltage. the voltage present at the t j pin is proportional to the junction temperature of the lt3992. the t j pin will be 250mv for a die temperature of 25c and will have a slope of 10mv/c.
lt3992 12 3992f a pplica t ions i n f or m a t ion choosing the output voltage the output voltage is programmed with a resistor divider between the output and the fb pin. choose the 1% resis- tors according to: r1 = r2 ? v out 0.806 C 1 ? ? ? ? ? ? r2 should be 10k or less to avoid bias current errors. ref- erence designators refer to the block diagram in figure 1. choosing the switching frequency the lt3992 switching frequency is set by resistor r3 in figure 1. the rt/sync pin is driven by a 12a current source. setting resistor r3 sets the voltage present at the rt/sync pin which determines the master oscillator frequency as illustrated in figure 2. the r3 resistance (in k) may be calculated from the desired switching frequency (in khz) by the equation: r3 = 1.86e-6 ? f sw 2 + 2.81e-2 ? f sw C1.76 for frequencies between 150khz and 2000khz. a 0v to 2.5v square wave with the same frequency as the master oscillator and in phase with channel 1 is output via the clkout pin. the clkout signal can be used to synchro- nize multiple switching regulators. figure 2. switching frequency vs rt/sync resistance rt/sync resistance (k) 0 0 clkout frequency (khz) 250 500 750 1500 1750 2000 2250 2500 20 40 50 80 3992 f02 1000 1250 10 30 60 70 to alleviate duty cycle restrictions due to minimum switch- on times, channel 1s switching frequency can be divided from the master clock by 1, 2, 4 or 8 determined by resistor r div in figure 1. channel 2s switching frequency is not affected by the div pin. the div pin is driven by a 12a current source. setting resistor r div sets the voltage pres- ent at the div pin which determines the divisor as shown in table 1. the div pin doesnt have any input hysteresis near the ratio thresholds. table 1. channel 1 divisor vs v div typical div voltage frequency ratio r div () v div < 0.5v 1 0 0.5v < v div < 1.0v 2 61.9k 1.0v < v div < 1.5v 4 102k 1.5v < v div 8 150k the switching frequency is typically set as high as pos- sible to reduce overall solution size. the lt3992 employs techniques to enhance dropout at high frequencies but efficiency and maximum input voltage decrease due to switching losses and minimum switch on times. the maximum recommended frequency can be approxi- mated by the equation: frequency (hz) = v out + v d v in C v sw + v d ? 1 t on(min) where v d is the forward voltage drop of the catch diode (d1 figure 2), v sw is the voltage drop of the internal switch, and t on(min) in the minimum on-time of the switch.
lt3992 13 3992f a pplica t ions i n f or m a t ion the following example along with the data in table 2 illustrates the trade-offs of switch frequency selection for a single input voltage system. example: v in = 25v, v out = 3.3v, i out = 2a, t on(min) = 180ns, v d = 0.6v, v sw = 0.4v. max frequency = 3.3 + 0.6 25 C 0.4 + 0.6 ? 1 180ns ~ 850khz rt/sync ~ 23.2k (figure 2 ) input v oltage range once the switching frequency has been determined, the input voltage range of the regulator can be determined. the minimum input voltage is determined by either the lt3992s minimum operating voltage of ~2.9v, or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on during a clock cycle. unlike most fixed frequency regulators, the lt3992 will not switch off at the end of each clock cycle if there is sufficient voltage across the boost capacitor (c3 in figure 1) to fully saturate the output switch. for cing switch off for a minimum time will only occur at the end of a clock cycle when the boost capacitor needs to be recharged. this operation has the same effect as lowering the clock frequency for a fixed off time, resulting in a higher duty cycle and lower minimum input voltage. the resultant duty cycle depends on the charging times of the boost capacitor and can be approximated by the following equation: dc max = 1 1 + 1 b where b is 3a divided by the typical boost current from the electrical characteristics table. this leads to a minimum input voltage of: v in(min) = v out + v d dc max C v d + v sw where v sw is the voltage drop of the internal switch. figure 4 shows a typical graph of minimum input voltage vs load current for the 3.3v output shown in figure 15. table 2. efficiency and size comparisons for different r rt/sync values, 3.3v output frequency (khz) rt/sync (k) efficiency v vin1/2 = 12v (%) v in(max) (v) ? l (h)* c (f)* c + l (area, mm2) 250 5.90 88 60 15 120 59.8 500 13.0 87 43 8.2 60 54.6 1000 28.0 84 21 3.3 30 51.9 1500 44.2 82 14 2.2 22 46.9 2250 69.8 78 9 1 15 19.1 ? v in(max) is defined as the highest typical input voltage that maintains constant output voltage ripple. * inductor and capacitor values chosen for stability and constant ripple current. figure 3. timing diagram rt/sync = 28.0k, t p = 1s, v div = 0v figure 4. minimum input voltage vs load current t p t p t p t p /2 t p /2 t dclkosw2 t dclkosw1 sw1 sw2 clkout 3992 f03 current (ma) 0 0 voltage (v) 1 2 3 4 6 500 1000 1500 2000 3992 f04 2500 35003000 5 v out = 3.3v start-up running
lt3992 14 3992f a pplica t ions i n f or m a t ion the maximum input voltage is determined by the absolute maximum ratings of the v in and bst pins and by the frequency and minimum duty cycle. the minimum duty cycle is defined as: dc min = t on(min) ? frequency maximum input voltage as: v in(max) = v out + v d dc min C v d + v sw note that the lt3992 will regulate if the input voltage is taken above the calculated maximum voltage as long as maximum ratings of the v in and bst pins are not violated. however operation in this region of input voltage will exhibit pulse skipping behavior. example: v out = 3.3v, i out = 1a, frequency = 1mhz, temperature = 25c, v sw = 0.1v, b = 50 (from boost characteristics specification), v d = 0.4v, t on(min) = 180ns: dc max = 1 1 + 1 50 = 98% v in(min) = 3.3 + 0.4 0.98 C 0.4 + 0.1 = 3.48v dc min = t on(min) ? frequency = 0.18 v in(max) = 3.3 + 0.4 0.18 C 0.4 + 0.1 = 20.2v in cases where multiple input voltages are present, or the v in /v out ratio for channel 1 is significantly different than channel 2, channel 1s frequency can be divided by a factor of 2, 4 or 8 from the programmed value by setting the div pin resistor to the appropriate value. dividing channel 1s frequency will increase the maximum input voltage by the same ratio. channel 1s external components will have to be chosen according to the resulting frequency. example: v out = 3.3v, i out = 1a, frequency = 1mhz, temperature = 25c, v sw = 0.1v, b = 50 (from boost characteristics specification), v d = 0.4v, t on(min) = 180ns. r div = 1.2k?. dc min1 = t on(min1) ? frequency/4 = 0.045 v in1(max) = 3.3 + 0.4 0.045 C 0.4 + 0.1 = > 60v inductor selection and maximum output current a good first choice for the lt3992 inductor value is: l = v out f where f is frequency in mhz and l is in h. with this value 3a of load current will be available over the entire input voltage range. the inductors rms cur - rent rating must be greater than your maximum load current and its saturation current should be higher than the maximum peak switch current, and will reduce the output voltage ripple. if the maximum load for a single channel is lower than 2.5a, then you can decrease the value of the inductor and operate with higher ripple current, or you can adjust the maximum switch current for the channel via the ilim pin. this allows you to use a physically smaller inductor, or one with a lower dcr resulting in higher efficiency. the peak inductor and switch current is: i sw(pk) = i l(pk) = i out + ? i l 2 figure 5. timing diagram rt/sync = 28.0k, t p = 1s, v div = 0.75v 2 ? t p t p t p 1/(2 ? t p ) t p /2 t dclkosw2 t dclkosw1 sw1 sw2 clkout 3992 f05
lt3992 15 3992f a pplica t ions i n f or m a t ion to maintain output regulation, this peak current must be less than the lt3992s switch current limit, ilim. ilim can be set between 1.8a and 4.6a for each channel via a resistor from the ilim pin to ground. the ilim pin is driven by a 12a current source. setting resistor r lim sets the voltage present at the ilim pin which determines the maximum switch current as illustrated in figure 6. the value for r lim must be greater than 42.2k. a capacitor from the ilim pin to ground, or a resistor divider from the output, can be used to limit the peak current during start-up. if a capacitor is used it must be discharged before power-up to ensure proper operation. referring to figure 6, as the peak current limit is reduced, slope compensation further reduces the peak current with increasing duty cycle. when the ilim pin is used to reduce the peak switch cur - rent, the equation for inductor choice becomes: l = 50 ? v out f ? r ilim where f is frequency in mhz, l in h and r in k. when the lt3992s input supplies are operated at different input voltages, an input capacitor sized for that channel should be placed as close as possible to the respective v in pins. a caution regarding the use of ceramic capacitors at the input. a ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. if power is applied quickly (for example by plugging the circuit into a live power source) this tank can ring, doubling the in - put voltage and damaging the lt3992. the solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. for details, see application note 88. output capacitor selection typically step-down regulators are easily compensated with an output crossover frequency that is 1/10 of the switch- ing frequency. this means that the time that the output capacitor must supply the output load during a transient step is ~2 or 3 switching periods. with an allowable 1% drop in output voltage during the step, a good starting value for the output capacitor can be expressed by: c vout = max load step frequency ? 0.01 ? v out example: v out = 3.3v, frequency = 1mhz, max load step = 2a. c vout = 2 1e6 ? 0.01 ? 3.3v = 60f the calculated value is only a suggested starting value. increase the value if transient response needs improvement or reduce the capacitance if size is a priority. the output capacitor filters the inductor current to generate an output with low voltage ripple. it also stores energy in order to satisfy transient loads and to stabilize the lt3992s control loop. the switching frequency of the lt3992 determines the value of output capacitance required. also, the current mode control loop doesnt require the presence of output capacitor series resistance (esr). for these reasons, you are free to use ceramic capacitors to achieve very low output ripple and small circuit size. figure 6. peak switch current vs ilim resistor ilim pin resistor (k) 40 1.0 peak switch current (a) 1.5 2.5 3.0 3.5 4.5 50 70 3992 f06 2.0 4.0 90 100 60 80 input capacitor selection bypass the inputs of the lt3992 circuit with a 4.7f or higher ceramic capacitor of x7r or x5r type. a lower value or a less expensive y5v type can be used if there is additional bypassing provided by bulk electrolytic or tantalum capacitors.
lt3992 16 3992f a pplica t ions i n f or m a t ion you can also use electrolytic capacitors. the esrs of most aluminum electrolytics are too large to deliver low output ripple. tantalum and newer, lower esr organic electrolytic capacitors intended for power supply use, are suitable and the manufacturers will specify the esr. the choice of capacitor value will be based on the esr required for low ripple. because the volume of the capacitor determines its esr, both the size and the value will be larger than a ceramic capacitor that would give you similar ripple per - formance. one benefit is that the larger capacitance may give better transient response for large changes in load current. table 3 lists several capacitor vendors. table 3 vendor type series taiyo yuden ceramic x5r, x7r avx ceramic x5r, x7r tantalum kemet tantalum ta organic al organic t491, t494, t495 t520 a700 sanyo ta/al organic poscap panasonic al organic sp cap tdk ceramic x5r, x7r catch diode the diode d1 conducts current only during switch-off time. use a schottky diode to limit forward voltage drop to increase efficiency. the schottky diode must have a peak reverse voltage that is equal to regulator input voltage and sized for average forward current in normal operation. average forward current can be calculated from: i d(avg) = i out v in ? v in C v out ( ) with a shorted condition, diode current will increase to the typical value determined by the peak switch current limit of the lt3992 set by the ilim pin. this is safe for short periods of time, but it would be prudent to check with the diode manufacturer if continuous operation under these conditions can be tolerated. bst pin considerations the capacitor and diode tied to the bst pin generate a voltage that is higher than the input voltage. in most cases a 0.47f capacitor and a small schottky diode (such as the bat41) will work well. to ensure optimal performance at duty cycles greater than 80%, use a 0.5a schottky diode (such as a mbr0560). almost any type of film or ceramic capacitor is suitable, but the esr should be <1? to ensure it can be fully recharged during the off time of the switch. the capacitor value can be approximated by: c bst = i out(max) ? v out 5 ? v in v out C 2 ( ) ? f where i out(max) is the maximum load current. figure 7 shows four ways to arrange the boost circuit. the bst pin must be more than 3v above the sw pin for full efficiency. generally, for outputs of 3.3v and higher the standard circuit (figure 7a) is the best. for lower output voltages the boost diode can be tied to the input (fig- ure 7b). the circuit in figure 7a is more efficient because the bst pin current comes from a lower voltage sour ce. figure 7c shows the boost voltage source from available dc sour ces that are greater than 3v. the highest efficiency is attained by choosing the lowest boost voltage above 3v. for example, if you are generating 3.3v and 1.8v and the 3.3v is on whenever the 1.8v is on, the 1.8v boost diode can be connected to the 3.3v output. in any case, you must also be sure that the maximum voltage at the bst pin is less than the maximum specified in the absolute maximum ratings section. the boost circuit can also run directly from a dc voltage that is higher than the input voltage by more than 3v, as in figure 7d. the diode is used to prevent damage to the lt3992 in case v x is held low while v in is present. the circuit saves several components (both bst pins can be tied to d2). however, efficiency may be lower and dissipa - tion in the lt3992 may be higher. also, if v x is absent, the lt3992 will still attempt to regulate the output, but will do so with very low efficiency and high dissipation because the switch will not be able to saturate, dropping 1.5v to 2v in conduction.
lt3992 17 3992f a pplica t ions i n f or m a t ion figure 7. bst pin considerations the minimum input voltage of an lt3992 application is limited by the minimum operating voltage (typically 2.9v) and by the maximum duty cycle as outlined above. for proper start-up, the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, or the lt3992 is turned on with its ss pin when the output is already in regulation, then the boost capacitor may not be fully charged. because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. the typical performance characteristics section shows plots of the minimum load current to start and to run as a function of input voltage for 3.3v outputs. in many cases the discharged output capacitor will present a load to the switcher which will allow it to start. the plots show the worst-case situation where v in is ramping very slowly. use a schottky diode for the lowest start-up voltage. outputs greater than 6v for outputs greater than 6v, add a resistor of 1k to 2.5k across the inductor to damp the discontinuous ringing of the sw node, preventing unintended sw current. the 24v output circuit in the typical applications section shows the location of this resistor. frequency compensation the lt3992 uses current mode control to regulate the output. this simplifies loop compensation. in particular, the lt3992 does not require the esr of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. frequency compensation is provided by the components tied to the v c pin. generally a capacitor and a resistor in series to ground determine loop gain. in addition, there is a lower value capacitor in parallel. this capacitor is not part of the loop compensation but is used to filter noise at the switching frequency. v in v in v x > v in + 3v bst gnd lt3992 sw ind v out v bst ? v sw = v x v bst(max) = v x v x(min) = v in + 3v v out < 3v 3992 f07 v in v in v x = lowest v in or v out > 3v bst gnd lt3992 sw ind v out v bst ? v sw = v x v bst(max) = v in + v x v x(min) = 3v v out < 3v c3 v in v in bst d2 gnd (7d) (7c) (7b) lt3992 sw ind v out v bst ? v sw = v in v bst(max) = 2 ??v in v out < 3v c3 v in v in bst d2 gnd (7a) lt3992 sw ind v out v bst ? v sw = v out v bst(max) = v in + v out v out c3 d2 d2
lt3992 18 3992f a pplica t ions i n f or m a t ion loop compensation determines the stability and transient performance. designing the compensation network is a bit complicated and the best values depend on the application and in particular the type of output capacitor. a practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the com- pensation network to optimize the performance. stability should then be checked across all operating conditions, including load current, input voltage and temperature. the lt1375 data sheet contains a more thorough discus - sion of loop compensation and describes how to test the stability using a transient load. figure 8 shows an equivalent circuit for the lt3992 control loop. the error amp is a transconductance amplifier with finite output impedance. the power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifier generating an output cur - rent proportional to the voltage at the v c pin. note that the output capacitor integrates this current, and that the capacitor on the v c pin (c c ) integrates the error amplifier output current, resulting in two poles in the loop. in most cases a zero is required and comes from either the output capacitor esr or from a resistor in series with c c . this simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. a phase lead capacitor (c pl ) across the feedback divider may improve the transient response. synchronization the rt/sync pin can also be used to synchronize the regulators to an external clock source. driving the rt/sync resistor with a clock source triggers the synchronization detection circuitry. once synchronization is detected, the rising edge of sw1 will be synchronized to the rising edge of the rt/sync signal and the rising edge of sw2 syn - chronized to the falling edge of the rt/sync signal (see figures 10 and 11). during synchronization, a 0v to 2.4v square wave with the same frequency and duty cycle as the synchronization signal is output via the clkout pin with a typical propagation delay of 250ns. in addition, an internal agc loop will adjust slope compensation to avoid subharmonic oscillation. if the synchronization signal is halted, the synchronization detection circuitry will timeout in typically 10s at which time the lt3992 reverts to the free-running frequency based on the rt/sync pin voltage. the synchronizing clock signal input to the lt3992 must have a frequency between 200khz and 2mhz, a duty cycle between 20% and 80%, a low state below 0.5v and a high state above 1.6v. synchronization signals outside of these parameters will cause erratic switching behavior. if the rt/sync pin is held above 1.6v at any time, switching will be disabled. if the synchronization signal is not present during regu- lator start-up (for example, the synchronization circuitry is powered from the regulator output) the rt/sync pin must remain below 1v until the synchronization circuitry is active for proper start-up operation. figure 8. model for loop response + + ? 0.806v lt3992 fb v c c f c pl output c1 c1 3992 f08 c c r c r1 esr tantalum or polymer ceramic r2 3.6m error amp g m = 400mho current mode power stage g m = 4.8mho
lt3992 19 3992f a pplica t ions i n f or m a t ion if the synchronization signal powers up in an undetermined state (v ol , v oh , hi-z), connect the synchronization clock to the lt3992 as shown in figure 9. the circuit as shown will isolate the synchronization signal when the output voltage is below 90% of the regulated output. the lt3992 will start up with a switching frequency determined by the resistor from the rt/sync pin to ground. if the synchronization signal powers up in a low impedance state (v ol ), connect a resistor between the rt/sync pin and the synchronizing clock. the equivalent resistance seen from the rt/sync pin to ground will set the start- up frequency. if the synchronization signal powers up in a high imped- ance state (hi-z), connect a resistor from the rt/sync pin to ground. the equivalent resistance seen from the rt/sync pin to ground will set the start-up frequency. figure 9. synchronous signal powered from regulators output figure 10. timing diagram rt/sync = 1mhz, duty cycle = 50% figure 11. timing diagram rt/sync = 1mhz, duty cycle > 50% lt3992 synchronization circuitry v out1 rt/sync 3992 f09 v cc clk pg1 t p t p t p t p /2 t p /2 t p t p /2 t dclkosw2 t drtsync t dclkosw1 sw1 sw2 clkout rt/sync 3992 f10 t p t dclkosw2 t dclkosw1 sw1 sw2 clkout rt/sync t drtsynch t drtsynch 3992 f11 t p t pon t pon t p t p
lt3992 20 3992f a pplica t ions i n f or m a t ion reducing input ripple voltage synchronizing the switches to the rising and falling edges of the synchronization signal provides the unique ability to reduce input ripple currents in systems where v in1 and v in2 are connected to the same supply. decreasing the input current ripple reduces the required input capacitance. for example, the input ripple voltage shown in figure 12 for a typical antiphase dual 14.4v to 8.5v and 14.4v to 3.3v regulator is decreased from a peak of 472mv to 160mv as shown in figure 13 by driving the lt3992 with a 71% duty cycle synchronization signal. shutdown and undervoltage/overvoltage lockout typically, undervoltage lockout (uvlo) is used in situa - tions where the input supply is current limited, or has a relatively high source resistance. a switching regulator draws constant power from the source, so source cur - rent increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. uvlo prevents the regulator from operating at source voltages where these problems might occur. an internal comparator will force both channels into shut - down below the minimum v in1 of 2.9v. this feature can be used to prevent excessive discharge of battery-operated systems. in addition to the v in1 undervoltage lockout, both channels will be disabled when shdn1 is less than 1.32v. programmable uvlo may be implemented using an input voltage divider and one of the internal comparators (see the typical applications section). when the shdn pin is taken above 1.32v, its respective channel is allowed to operate. when the shdn pin is driven below 1.32v, its channel is placed in a low quiescent current state. there is no hysteresis on the shdn pins. keep the connections from any series resistors to the shdn pins short and make sure that the interplane or surface capacitance to switching nodes is minimized. soft-start the output of the lt3992 regulates to the lowest voltage present at either the ss pin or an internal 0.806v reference. a capacitor from the ss pin to ground is charged by an internal 12a current source resulting in a linear output ramp from 0v to the regulated output whose duration is given by: t ramp = c ss ? 0.806v 12a at power-up, a reset signal sets the soft-start latch and discharges both ss pins to approximately 0v to ensure proper start-up. when both ss pins are fully discharged the latch is reset and the internal 12a current source starts to charge the ss pin. figure 12. dual 14.4v/8.5v, 14.4v/3.3v with 180 phase figure 13. dual 14.4v/8.5v, 14.4v/3.3v with 256 phase sw1 sw2 rt/sync 3992 f12 input ripple v sw1 sw2 rt/sync input ripple v 3992 f13
lt3992 21 3992f a pplica t ions i n f or m a t ion when the ss pin voltage is below 110mv, the v c pin is pulled low which disables switching. this allows the ss pin to be used as an individual shutdown for each channel. as the ss pin voltage rises above 110mv, the v c pin is released and the output is regulated to the ss voltage. when the ss pin voltage exceeds the internal 0.806v reference, the output is regulated to the reference. the ss pin voltage will continue to rise until it is clamped at typically 2.15v. in the event of a v in1 undervoltage lockout, the soft-start latch is set for both channels, triggering a full start-up sequence. if a channels shdn pin is driven below 1.32v, its overvoltage lockout is enabled, or the internal die temperature for its power switch exceeds its maximum rating during normal operation, the soft-start latch is set for that channel. in addition, if the load exceeds the maximum output switch current, the output will start to drop causing the v c pin clamp to be activated. as long as the v c pin is clamped, the ss pin will be discharged. as a result, the output will be regulated to the highest voltage that the maximum output current can support. for example, if a 6v output is loaded by 1? the ss pin will drop to 0.46v, regulating the output at 4.6v ( 4.6a ? 1? ). once the overload condition is removed, the output will soft start from the temporary voltage level to the normal regulation point. since the ss pin is clamped at typically 2.15v and has to discharge to 0.806v before taking control of regulation, momentary overload conditions will be tolerated without a soft-start recovery. the typical time before the ss pin takes control is: t ss(control) = c ss ? 1.2v 0.9ma open-collector comparators the cmpo pin is the open-collector output of an internal comparator. the comparator compares the cmpi pin volt - age to 90% of the reference voltage (0.72v) with 80mv of hysteresis. the cmpo pin has a typical sink capability of 250a when the cmpi pin is below the threshold and can withstand 60v when the threshold is exceeded. the cmpo pin is active (sink capability is reduced in shutdown and undervoltage lockout mode) as long as the v in1 pin voltage exceeds typically 2.9v. the comparators can be used to monitor input and output voltages as well as die temperature. see the typical ap - plications circuit collection for examples. output tracking/sequencing complex output tracking and sequencing between channels can be implemented using the lt3992s ss and cmpo pins. figure 14 shows several configurations for output tracking/sequencing for a 3.3v and 1.8v application. independent soft-start for each channel is shown in fig- ure?14a. the output ramp time for each channel is set by the soft-start capacitor as described in the soft-start section. ratiometric tracking is achieved in figure 14b by con - necting both ss pins together. in this configuration, the ss pin source current is doubled (24a) which must be taken into account when calculating the output rise time. by connecting a feedback network from v out1 to the ss2 pin with the same ratio that sets v out2 voltage, absolute tracking shown in figure 14c is implemented. the mini - mum value of the top feedback resistor (r1) should be set such that the ss pin can be driven all the way to ground with 0.9ma of sink current when v out1 is at its regulated voltage. in addition, a small v out2 voltage offset will be present due to the ss2 12a source current. this offset can be corrected for by slightly reducing the value of r2. figure 14d illustrates output sequencing. when v out1 is within 10% of its regulated voltage, cmpo1 releases the ss2 soft-start pin allowing v out2 to soft-start. in this case cmpo1 will be pulled up to 2v by the ss pin. if a greater voltage is needed for cmpo1 logic, a pull-up resistor to v out1 can be used. this will decrease the soft-start ramp time and increase tolerance to momentary shorts. if precise output ramp up and down is required, drive the ss pins as shown in figure 14e. the minimum value of resistor (r3) should be set such that the ss pin can be driven all the way to ground with 0.9ma of sink current during power-up and fault conditions.
lt3992 22 3992f a pplica t ions i n f or m a t ion figure 14. ss pin configurations + ? v out1 fb1 cmpi1 cmpo1 lt3992 ss1 0.1f 0.22f 0.72v 2.5v 12a r1 r2 pg1 pg2 r3 5ms/div independent start-up (14a) v out1 0.5v/div v out2 0.5v/div + ? v out2 fb2 cmpi2 cmpo2 0.72v r4 r5 r6 ss2 2.5v 12a pg1 pg2 + ? v out1 fb1 cmpi1 cmpo1 lt3992 ss1 0.1f 0.22f 0.72v 2.5v 12a r1 r2 pg1 pg2 10ms/div output sequencing (14d) v out1 0.5v/div v out2 0.5v/div + ? v out2 fb2 cmpi2 cmpo2 0.72v r4 r5 r6 ss2 2.5v 12a pg1 pg2 + ? v out1 fb1 cmpi1 cmpo1 lt3992 ss1 r5 0.72v 2.5v 12a r1 r2 r3 pg1 10ms/div controlled power up and down (14e) v out1 0.5v/div v out2 0.5v/div + ? v out2 fb2 cmpi2 cmpo2 0.72v r4 r5 3992 f14 r6 pg2 ss2 2.5v 12a pg1/pg2 ss1/2 + ? v out1 fb1 cmpi1 cmpo1 lt3992 ss1 0.1f 0.72v 2.5v 12a r1 r2 r3 pg1 pg2 10ms/div ratiometric start-up (14b) v out1 0.5v/div v out2 0.5v/div + ? v out2 fb2 cmpi2 cmpo2 0.72v r4 r5 r6 ss2 2.5v 12a pg1 pg2 + ? v out1 fb1 cmpi1 cmpo1 lt3992 ss1 0.1f r8 r7 0.72v 2.5v 12a r1 r2 r3 pg1 pg2 10ms/div absolute start-up (14c) v out1 0.5v/div v out2 0.5v/div + ? v out2 fb2 cmpi2 cmpo2 0.72v r4 r5 r6 ss2 2.5v 12a pg1 pg2 + ?
lt3992 23 3992f application optimization in multiple channel applications requiring large v in to v out ratios, the maximum frequency and resulting in - ductor size is determined by the channel with the largest ratio. the lt3992s multi-frequency operation allows the user to minimize component size for each channel while maintaining constant frequency operation. the circuit in figure 15 illustrates this approach. a 2-stage step-down approach coupled with multi-frequency operation will further reduce external component size by allowing an increase in frequency for the channel with the lower v in to v out ratio. the drawback to this approach is that the output power capability for the first stage is determined by the output power drawn from the second stage. the dual step-down application in figure 16 steps down the input voltage (v in1 ) to the highest output voltage then uses that voltage to power the second output (v in2 ). v out1 must be able to provide enough current for its output plus v out2 maximum load. note that the v out1 voltage must be above v in2 s minimum input voltage as specified in the electrical characteristics (typically 2.9v) when the second channel starts to switch. delaying channel 2 can be accomplished by either independent soft-start capacitors or sequencing with the cmp01 output. for example, assume a maximum input of 60v: v in = 60v, v out1 = 3.3v at 1.5a and v out2 = 12v at 1.5a. frequency (hz) = v out + v d v in C v sw + v d ? 1 t on(min) l = v in C v out ( ) ? v out v in ? f single step-down: frequency (hz) = 3.3 + 0.6 60v C 0.4 + 0.6 ? 1 180ns ? 350khz l1 = 60v C 3.3 ( ) ? 3.3 60v ? 350khz 9h l2 = 60v C 12 ( ) ? 12 60v ? 350khz 27h 2-stage step-down: frequency (hz) = 12 + 0.6 60v C 0.4 + 0.6 ? 1 180ns ? 1mhz l1 = 60v C 12 ( ) ? 12 60v ? 1mhz 10h l2 = 12 C 3.3 ( ) ? 3.3 12 ? 1mhz 2.4h 2-stage step-down multi-frequency: r div = 61.9k, freq1 = 900khz, freq2 = 1800khz. l1 = 60v C 12 ( ) ? 12 60v ? 900khz 11h l2 = 12 C 3.3 ( ) ? 3.3 12 ? 1800kh z 1.3h in addition, r ilim2 = 52.3k reduces the peak current limit on channel 2 to 2.5a, which reduces inductor size and catch diode requirements. a pplica t ions i n f or m a t ion
lt3992 24 3992f figure 15. 12v and 3.3v dual step-down multi-frequency converter a pplica t ions i n f or m a t ion bst1 sw1 v out1 cmpi1 cmpo1 ss1 ilim1 i lim1 rt/sync div v c1 fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 clkout v c2 t j fb2 ind2 3992 f15 bst2 shdn1 shdn2 v in1 lt3992 gnd v in2 4.7f 4.7f v in1 15v to 60v v out2 12v 1.5a 400khz v out1 v out1 3.3v 1.5a 200khz 100k pg1 22h 22h 0.47f 0.22f 8.06k 61.9k 13k 60.4k 1000pf 33pf 0.1f 10k 680pf 0.1f 33pf 15k 113k 10nf clkout 400khz 8.06k 24.9k 100f 2 47f 100k pg2 figure 16. 12v and 3.3v 2-stage multi-frequency step-down converter bst1 sw1 v out1 cmpi1 cmpo1 ss1 ilim1 ilim1 rt/sync div v c1 fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 clkout v c2 t j fb2 ind2 3992 f16 bst2 shdn1 shdn2 v in1 v out2 lt3992 gnd v in2 4.7f v in1 15v to 60v v out2 3.3v 2a 1600khz v out1 12v 1a 400khz 100k pg 22h 2.2h 0.1f 0.1f 8.06k 102k 15k 60.4k 680pf 33pf 0.1f 48.7k 470pf 0.1f 33pf 16k 24.9k fb1 10nf clkout 1600khz 8.06k 113k 10f 47f
lt3992 25 3992f a pplica t ions i n f or m a t ion figure 17. diode d4 prevents a shorted input from discharging a backup battery tied to the output figure 18. subtracting the current when the switch is on (18a) from the current when the switch is off (18b) reveals the path of the high frequency switching current (18c). keep this loop small. the voltage on the sw and bst traces will also be switched; keep these traces as short as possible. finally, make sure the circuit is shielded with a local ground plane shorted and reverse input protection if the inductor is chosen so that it wont saturate exces- sively, an lt3992 step-down regulator will tolerate a shorted output. there is another situation to consider in systems where the output will be held high when the input to the lt3992 is absent. this may occur in battery charging applications or in battery back-up systems where a battery or some other supply is diode or-ed with the lt3992s output. if the v in1/2 pin is allowed to float and the shdn pin is held high (either by a logic signal or because it is tied to v in ), then the lt3992s internal circuitry will pull its quiescent current through its sw pin. this is fine if your system can tolerate a few ma in this state. if you ground the shdn pin, the sw pin current will drop to essentially zero. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the lt3992 can pull large currents from the output through the sw pin and the v in1/2 pin. figure 17 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. v in gnd (18a) lt3992 sw v in gnd (18c) lt3992 sw 3992 f18 v in gnd (18b) lt3992 sw v in v in1/2 v out1/2 sw lt3992 d4 parasitic diode 3992 f17 pcb layout for proper operation and minimum emi, care must be taken during printed circuit board (pcb) layout. figure 18 shows the high di/dt paths in the buck regulator circuit. note that large switched currents flow in the power switch, the catch diode and the input capacitor. the loop formed by these components should be as small as possible. these components, along with the inductor and output capacitor, should be placed on the same side of the cir - cuit board and their connections should be made on that layer. place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the out- put capacitor c2. route all small signal analog returns to the ground connection at the bottom of the package. additionally, the sw and bst traces should be kept as short as possible.
lt3992 26 3992f a pplica t ions i n f or m a t ion thermal considerations the pcb must also provide heat sinking to keep the lt3992 cool. the exposed metal on the bottom of the package must be soldered to a ground plane. this ground should be tied to other copper layers below with thermal vias; these layers will spread the heat dissipated by the lt3992. place additional vias near the catch diodes. adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can further reduce thermal resistance. the topside metal and component outlines in figure 19 illustrate proper component placement and trace routing. the lt3992s powerful 4.6a switches allow the converter to source large output currents. depending on the con - verters operating conditions, the resulting internal power dissipation can raise the junction temperature beyond its maximum rating. operating conditions include input voltages, output voltages, switching frequencies, output currents, and the ambient environmental temperature, etc. an estimation of the junction temperature rise above ambient temperature helps determine whether a given design may exceed the maximum junction ratings for specific operating conditions. however, temperature rise depends on pcb design and the proximity to other heat sources. the final converter design must be evaluated on the bench. figure 19. pcb top layer and component placement for tssop and qfn packages 3992 f19
lt3992 27 3992f a pplica t ions i n f or m a t ion an estimation of the junction temperature rise begins by determining which circuit components dissipate power. in order to simplify the power loss estimation, only the inductors, catch diodes, and the lt3992 will be considered as heat sources. after the operating conditions have been determined, the individual power losses are calculated by: power d1,2 = 1 ? v out v in ? ? ? ? ? ? ? i out ? v fd power ind1,2 = r ind ? i out 2 power ch1,2 = 0.1 ? v out v in ? i out 2 + 2 ? 10 C3 ? v in + i out ? v out ? v boost 40 ? v in + v in ? i out ? f sw ? 10 ? 6 ? v in 2.5 + i out 0.25 ? ? ? ? ? ? where: f sw = switching frequency in khz r ind = inductor re sis tan ce v fd = catch diode forward voltage drop v boost = switch boost voltage for the lt3992 demo board using the tssop package, the estimated junction temperature rise above ambient temperature is found by: t risetssop 10 ? (power d1 + power d2 ) + 12.3 ? (power ind1 + power ind2 ) + 17.5 ? power ch1 + power ch2 ( ) the estimated junction temperature rise above ambient for the lt3992 qfn layout is: t riseqfn 8.5 ? (power d1 + power d2 ) + 13 ? (power ind1 + power ind2 ) + 23 ? power ch1 + power ch2 ( ) for example, the typical application circuits listed in table 4 are used to calculate the individual power loss contribu- tions in table 5. table 6 shows the estimated power loss and junction temperature rise above ambient temperature. note that the larger tssop package demonstrates better thermal performance than the compact qfn package on the lt3992 demo circuit boards. for lt3992 applications that favor thermal performance, the tssop package is the preferred package option. table 4 application v in1 (v) v in2 (v) f sw ch1 f sw ch2 v out1 (v) i out1 (a) v out2 (v) i out2 (a) front page 48 12 400 1600 12 1.5 5 2 back page 48 48 300 300 5 2 3 2 table 5 application pd1 (w) pd2 (w) pl1 (w) pl2 (w) pch1 (w) pch2 (w) front page 0.54 0.56 0.23 0.28 0.99 0.79 back page 0.88 0.92 0.28 0.2 0.95 0.91 table 6 p loss (w) t rise tssop (c) t rise qfn (c) application calc meas calc meas calc meas front page 3.38 3.2 48.3 46.1 56.8 53.3 back page 4.14 4.2 56.4 53.0 64.3 62.9 the power loss and temperature rise equations provided in the thermal considerations section serve as a good starting point for estimating the junction temperature rise. however, the lt3992 is a very versatile converter. the combination of independent input voltages, output voltages, output currents, switching frequencies, and package selections for the lt3992 dictate that no power loss estimation scheme can accommodate every possible operating condition. as such, it is absolutely necessary to evaluate a converters performance at the bench. the power dissipation in the other power components such as boost diodes, input and output capacitors, inductor core loss, and trace resistances cause additional copper heating and can further increase what the ic sees as am- bient temperature. see the lt1767 data sheets thermal considerations section.
lt3992 28 3992f a pplica t ions i n f or m a t ion die temperature and thermal shutdown the lt3992 t j pin outputs a voltage proportional to the internal junction temperature. the t j pin typically outputs 250mv for 25c and has a slope of 10mv/c. without the aid of external circuitry, the t j pin output is valid from 20c to 150c (200mv to 1.5v) with a maximum load of 100a. full temperature range measurement to extend the operating temperature range of the t j out- put below 20c, connect a resistor from the t j pin to a negative supply as shown in figure 20. the negative rail voltage and t j pin resistor may be calculated using the following equations: v neg 2 ? temp(min) c 100 r1 | v neg | 33a where: temp(min)c is the minimum temperature where a valid t j pin output is required. v neg = regulated negative voltage supply. for example: temp(min)c = C40c v neg C0.8v v neg = C1, r1 |v neg |/33a = 30.2k figure 20. circuit to extend the t j pin operating range figure 21. circuit to generate the negative voltage rail to extend the t j pin operating range generating a negative regulated voltage the simple charge pump circuit in figure 21 uses the clkout pin output to generate a negative voltage, elimi- nating the need for an external regulated supply. surface mount capacitors and dual-package schottky diodes minimize the board area needed to implement the nega- tive voltage supply. as a safeguard, the lt3992 has an additional thermal shutdown threshold set at a typical value of 163c for each channel. each time the threshold is exceeded, a power on sequence for that channel will be initiated. the sequence will then repeat until the thermal overload is removed. it should be noted that the t j pin voltage represents a steady-state temperature and should not be used to guarantee that maximum junction temperatures are not exceeded. instantaneous power along with thermal gradients and time constants may cause portions of the die to exceed maximum ratings and thermal shutdown thresholds. be sure to calculate die temperature rise for steady state (>1min) as well as impulse conditions. lt3992 30k 330pf 0.1f d3, d4: zetex bat54s d4 d3 gnd 3992 f21 t j clkout + lt3992 r1 v neg gnd 3992 f20 t j
lt3992 29 3992f clkout capacitive loading a minor drawback to generating a negative rail from the clkout pin is that the charge pump adds capacitance to the clkout pin, resulting in an output synchronization clock signal phase delay. figures 22 and 23 show the im - pact of capacitive loading on the clkout signal rise and fall times. note that a typical 10:1 150mhz oscilloscope probe contributes significant capacitance to the clkout node, necessitating a low capacitance probe for accurate measurements. applications requiring clkout to generate the negative supply voltage and provide the synchroniza- tion clock to other regulators may benefit from buffering clkout prior to the charge pump circuitry. other linear technology publications application notes 19, 35 and 44 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. design note dn100 shows how to generate a dual (+ and C) output supply using a buck regulator. a pplica t ions i n f or m a t ion figure 22. clkout rise time figure 23. clkout fall time 500mv/div 40ns/div 3992 f22 frequency: 1.000mhz charge pump scope probe: 15pf synchronized lt3992 rt/sync pin fet probe: 2pf 500mv/div 20ns/div 3992 f23 frequency: 1.000mhz charge pump scope probe: 15pf fet probe: 2pf synchronized lt3992 rt/sync pin
lt3992 30 3992f typical a pplica t ions quad output 5v, 2.5v, 1.8v and 1.2v multi-frequency synchronized, 2-stage converter with output sequencing, absolute tracking and current limiting bst1 sw1 v out1 cmpi1 cmpo1 ss1 ilim1 v c1 rt/sync div fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 v c2 clkout t j fb2 ind2 0.47f 4.7f 1f 1f 1f 47f 42.2k 0.1f 1000pf 33pf 470pf 33pf 10nf 8.06k 8.06k 34.8k 102k 11.8k 16.9k 42.2k 8.06k clockout 1200khz 10k 8.06k 4.02k 100k v in 7v to 60v v out1 5v 1.5a 300khz 15h bst2 shdn1 shdn2 v in1 lt3992 gnd v in2 0.1f 100pf 0.1f 47f 100k 16.9k v out2 2.5v 1a 1200khz pg 2.2h bst1 sw1 v out1 cmpi1 cmpo1 ss1 ilim1 v c1 rt/sync div fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 v c2 clkout t j fb2 ind2 0.1f 4.02k 100pf 100f 470pf 33pf 470pf 33pf 10nf 8.06k 8.06k 10k 15k 42.2k 3992 ta02 42.2k v out3 1.2v 1a 1200khz 2.2h bst2 shdn1 shdn2 v in1 lt3992 gnd v in2 0.1f 100pf 47f 10k v out4 1.8v 1a 1200khz 2.2h
lt3992 31 3992f t ypical applica t ions 24v and 5v 2-stage dual step-down converter bst1 sw1 v out1 cmpi1 cmpo1 ss1 ilim1 rt/sync div v c1 fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 clkout v c2 t j fb2 ind2 3992 ta03 bst2 shdn1 shdn2 v in1 v out2 lt3992 gnd v in2 4.7f v in1 25v to 60v v out2 5v 2a 1mhz v out1 24v 0.5a 1mhz 100k pg 22h 4.7h 0.1f 0.1f 8.06k 28k 42.2k 470pf 33pf 0.1f 28k 680pf 0.1f 33pf 100k 10k 42.2k fb1 10nf clkout 1mhz 8.06k 232k 10f 2k 47f 3.3v/5a single output with uvlo and power good sw1 v out1 cmpo1 cmpi1 ss1 ilim1 v c1 rt/sync div fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 v c2 clkout clkout 1mhz t j fb2 ind2 4.7f 2 820pf 10nf 33pf 0.1f 28k 20k 60.4k 3992 ta04 v in 5v to 18v 60v transient bst1 bst2 shdn1 shdn2 v in1 lt3992 gnd v in2 0.22f 47f 2 100k pg 8.06k 24.9k v out 3.3v 5a 2mhz effective ripple 4.7h 0.22f 4.7h 130k 374k
lt3992 32 3992f t ypical applica t ions power supply dual input single 3.3v/4a output step-down converter 5v and 1.8v dual 2-stage converter sw1 v out1 cmpo1 cmpi1 lim1 ss1 v c1 rt/sync t j fb1 ind1 sw2 v out2 cmpi2 cmpo2 lim2 ss2 v c2 clkout clkout 2mhz div fb2 ind2 4.7f 680pf 10nf 33pf 0.1f 61.9k 61.9k 21k 42.2k 64.9k 3992 ta05 v in1 12v bst1 bst2 shdn1 shdn1 shdn2 v in1 lt3992 gnd v in2 0.22f 47f 8.06k 24.9k v out 3.3v 4a v in2 5v 2.2h 0.22f 2.2h 13k 47.5k 1f bst1 sw1 v out1 cmpi1 cmpo1 ss1 ilim1 ilim1 v c1 rt/sync div fb1 fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 v c2 clkout clockout 1600khz t j fb2 ind2 0.22f 4.7f 42.2k 100k 22f 0.1f 820pf 33pf 33pf 10nf 8.06k 8.06k 48.7k 102k 13k 0.1f 3992 ta06 21k 470pf 21k v in1 7v to 60v v out1 5v 1a 400khz pg 15h bst2 shdn1 shdn2 v in1 lt3992 gnd v in2 0.22f 100pf 47f 10k v out2 1.8v 1a 1600khz 2.2h 1f
lt3992 33 3992f t ypical applica t ions 12v, 3.3v and 1.2v triple output with external synchronization, output sequencing and tracking sw1 v out1 cmpo1 cmpi1 ss1 ilim1 v c1 rt/sync div fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 v c2 clkout clkout 1mhz t j fb2 ind2 2.2f 2 1300pf 10nf 33pf 0.1f 28k 7.5k 22.1k 3992 ta07 v in 13v to 60v bst2 shdn1 shdn2 bst1 v in1 lt3992 gnd v in2 0.22f 22f 2 200k pg 8.06k 113k 22h 0.22f 22h 0.1f 133k v + out1 ltc6908-1 out2 mod gnd set bst1 sw1 v out1 cmpi1 cmpo1 ss1 ss1 ilim1 v c1 rt/sync div fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 v c2 clkout t j fb2 ind2 0.1f 1f 4.02k 100f 2 100pf 0.1f 1000pf 33pf 470pf 10nf 8.06k 8.06k 61.9k 7.68k 16k 100k 33pf 100k v out3 v out2 1.2v 3a 500khz v out2 v out1 12v 0.5a 1mhz 2.2h bst2 shdn1 shdn1 shdn1 shdn2 v in1 lt3992 gnd v in2 0.1f 100pf 100f 24.9k v out3 3.3v 3a 1mhz 2.2h 1f offon
lt3992 34 3992f p ackage descrip t ion 4.75 (.187) ref fe38 (aa) tssop rev c 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev c) exposed pad variation aa please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
lt3992 35 3992f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
lt3992 36 3992f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0312 ? printed in usa r ela t e d p ar t s typical a pplica t ion fmea fault tolerant 5v/2a and 3.3v/2a dual converter part number description comments lt3692/ lt3692a 36v, dual 3.5a, 2.25mhz high efficiency step-down dc/dc converter v in = 3v to 36v, v out(min) = 0.8v, i q = 4ma, i sd < 10a, 5mm 5mm qfn-32, tssop-38e lt3507/ LT3507A 36v, triple 2.4a, 1.4a and 1.4a (i out ), 2.5mhz, high efficiency step-down dc/dc converter with ldo controller v in = 4v to 36v, v out(min) = 0.8v, i q = 7ma, i sd = 1a, 5mm 7mm qfn-38 lt3508 36v with transient protection to 40v, dual 1.4a (i out ), 3mhz, high efficiency step-down dc/dc converter v in = 3.7v to 37v, v out(min) = 0.8v, i q = 4.6ma, i sd = 1a, 4mm 4mm qfn-24, tssop-16e lt3680 36v, 3a, 2.4mhz high efficiency micropower step-down dc/dc converter v in = 3.6v to 36v, v out(min) = 0.8v, i q = 75a, i sd < 1a, 3mm 3mm dfn-10, msop-10e lt3693 36v, 3a, 2.4mhz high efficiency step-down dc/dc converter v in = 3.6v to 36v, v out(min) = 0.8v, i q = 1.3ma, i sd < 1a, 3mm 3mm dfn-10, msop-10e lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode ? operation v in = 3.6v to 38v, transients to 60v, v out(min) = 0.78v, i q = 70a, i sd < 1a, 3mm 3mm dfn-10, msop-10e lt3980 58v with transient protection to 80v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode operation v in = 3.6v to 58v, transients to 80v, v out(min) = 0.79v, i q = 75a, i sd < 1a, 3mm 4mm dfn-16, msop-16e lt3971 38v, 1.2a (i out ), 2mhz, high efficiency step-down dc/dc converter with only 2.8a of quiescent current v in = 4.2v to 38v, v out(min) = 1.2v, i q = 2.8a, i sd < 1a, 3mm 3mm dfn-10, msop-10e lt3991 55v, 1.2a (i out ), 2mhz, high efficiency step-down dc/dc converter with only 2.8a of quiescent current v in = 4.2v to 55v, v out(min) = 1.2v, i q = 2.8a, i sd < 1a, 3mm 3mm dfn-10, msop-10e bst1 sw1 v out1 cmpi1 cmpo1 ss1 ilim1 rt/sync div v c1 fb1 ind1 sw2 v out2 cmpi2 cmpo2 ss2 ilim2 ss2 ilim2 clkout v c2 t j fb2 ind2 3992 ta08 bst2 shdn1 shdn2 shdn2 v in1 lt3992 gnd v in2 4.7f 4.7f 100k v in1 6v to 60v v out2 3.3v 2a 300khz v out1 5v 2a 300khz 249k pg 15h 10h 0.47f 0.47f 806 11.8k 1000pf 33pf 33pf 7.15k 1000pf 100nf 60.4k 12.1k 2.49k 10nf clkout 300khz 806 4.22k 100f 100k 100k 100f 10nf 249k pg2

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